/** @file
Define MCU information parsing and retrieval interfaces.

Copyright (C) 2022 - 2023, Phytium Technology Co., Ltd. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/
#ifndef MCU_INFO_H_
#define MCU_INFO_H_

#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ParameterTable.h>
#include <Library/PcdLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugLib.h>
#include <Library/I2cLib.h>
#include <Library/I3cBusLib.h>
#include <Library/CrcLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PssiLib.h>
#include <Library/PhytiumPostCodeLib.h>


#define CPU_ID_64C 0x800
#define CPU_ID_32C 0x810
#define CPU_ID_16C 0x820

//
//Infor abort DDR5
//
#define VR_ENABLE 0x32

#define ONE_DIE_ONE_DIMM        0x1 /* also apply to twodieonedimm  fourdieonedimm*/
#define ONE_DIE_TWO_DIMM        0x3
#define TWO_DIE_TWO_DIMM        0x5
#define TWO_DIE_FOUR_DIMM       0xF
#define FOUR_DIE_FOUR_DIMM      0x55
#define FOUR_DIE_EIGHT_DIMM     0xFF
#define EIGHT_DIE_EIGHT_DIMM    0x5555
#define EIGHT_DIE_SIXTEEN_DIMM  0xFFFF

#define SPD_MTB                   125     //125ps
#define SPD_FTB                   1       //1ps

#define RDIMM_TYPE                1
#define UDIMM_TYPE                2
#define SODIMM_TYPE               3
#define LRDIMM_TYPE               4
#define DIMM_X4                   0x0
#define DIMM_X8                   0x1
#define DIMM_X16                  0x2
#define DIMM_X32                  0x3
#define MIRROR                    0x1
#define NO_MIRROR                 0x0
#define ECC_TYPE                  1
#define NO_ECC_TYPE               0
#define ROW_NUM                   16
#define COL_NUM                   10
#define DDR3_TYPE                 0xB
#define DDR4_TYPE                 0xC
#define LPDDR4_TYPE               0x10
#define DDR5_TYPE                 0x12

#define SAMSUNG_VENDOR            0x80CE
#define HYNIX_VENDOR              0x80AD
#define MICRON_VENDOR             0x802C
#define KINGSTON_VENDOR           0x0198
#define RAMAXEL_VENDOR            0x0443
#define LANQI_VENDOR              0x8632
#define CXMT_VENDOR               0x8A91
#define UNILC_VENDOR              0x081A

#define SPD_BYTE_NUMBER_DDR5      1024
#define BYTES_EVERY_PAGE_DDR5     128

#define SPD_BYTE_NUMBER_DDR4      512
#define BYTES_EVERY_PAGE_DDR4     256

#define LMU0_I2C_ID               0
#define LMU1_I2C_ID               0
#define LMU0_I2C_SLAVE_ADDR       0x50
#define LMU1_I2C_SLAVE_ADDR       0x51

VOID
GetDdrConfigParameter (
  IN OUT  PARAMETER_DDR_CONFIG_V3 *DdrConfigData
  );

#endif /* MCU_INFO_H_ */
